Simulation of 4H-SiC VJFET
TCAD simulations rely on physical models describing the operational phenomena and model parameters calibrated to the process and materials used to fabricate the devices. In a previous article, we compiled the key material and model parameters for the 4HsiC polytype [8]. In this article, we perform simulations of a 4H-SiC trenched-andimplanted VJFET, a type of device that holds commercial promise. The device structure and experimental data are from Zhao et al. [9].
The VJFET structure allows the realization of ‘normally off’ devices, which are de-sirable for fail-safe protection. The device structure is defined in Sentaurus Structure Editor and is shown in Figure 1. The device is created on the Si face of the 4H-SiC material and has an n- vertical channel and drift region with a doping concentration of 6.5 x 1015 cm–3. The p+ gate regions, with a doping concentration of 1.0 x 1018 cm–3, are created on the sidewalls of the trenches. The p++ contact regions have a doping concentration of 5.0 x 1019 cm–3.
The n+ substrate, above the drain contact, is doped with a concentration of 6.0 x 1018 cm–3, and the n+ source region has a concentration of 1.0 x 1018 cm–3. The trench region comprises a 50-nm thick thermal oxide, followed by a 200-nm thick sili-
«Fig. 1»Device structure and doping profile of VJFET.
«Fig. 2»Simulation mesh of VJFET. Inset shows mesh refinement surrounding the critical regions at the bottom of the vertical channel.
con nitride layer, and the remaining portion is filled with oxide. The vertical channel is designed to have an opening of 0.63 μm, and the blocking layer or the n- drift region is designed to have a thickness of approximately 9.4 μm.
Figure 2 shows the meshed VJFET structure. The inset shows a finely meshed p-n junction region and parts of the vertical channel. Such a refinement is needed to resolve properly the space-charge regions and to capture accurately the impact ionization effects for breakdown simulation. These meshing constraints can be easily implemented in Sentaurus Structure Editor using either its graphical user interface or its powerful scripting capabilities.
Electrical simulations are performed with Sentaurus Device using physical models incorporating:
· Doping-dependent and temperaturedependent Shockley–Read–Hall (SRH) recombination and Auger processes.
· Doping-dependent mobility models with high-field velocity saturation effects.
· Impact ionization (Okuto–Crowell model).
Sentaurus Device accounts for the anisotropic properties of 4H-SiC resulting from the hexagonal crystal structure. Table 1 lists some important model parameters used in the simulations for mobility and impact ionization.
Table 1
Important model parameters used in the simulations for mobility and impact ionization.
| Model Parameter Coefficients | ||||
| Mobility | ||||
| For Electrons | For Holes | Unit | Reference | |
| MuMax | cm2/(Vs) | 10] | ||
| Anisotropic Mobility | ||||
| MuMax | cm2/(Vs) | [7][11] | ||
| Impact Ionization | G = alpha * exp( -beta / E) | |||
| alpha | 2.10e+07 | 2.96e+07 | 1/cm | [12] |
| beta | 1.70e+07 | 1.60e+07 | V/cm | |
| Anisotropic Impact Ionization | ||||
| alpha | 1.76e+07 | 3.41e+08 | 1/cm | [12] |
| beta | 3.30e+07 | 2.50e+07 | V/cm |
Simulation results for a single-cell VJFET with an active area of 320 μm x 293 μm, showing Idrain versus Vdrain characteristics for various gate biases, are presented in Figure 3.
Figure 4 shows the breakdown characteristics for the same device, as well as the region of the device undergoing acute avalanche generation. The simulated results show good agreement with experimental data.
«Fig.3»Measured (points) and simulated (lines) Ids–Vds characteristics of VJFET. Gate voltages in parentheses are the actual gate voltages. The discrepancy is due to gate contact resistance, which is not explicitly considered in the simulation [9].
«Fig. 4»Measured and simulated breakdown voltage.
References
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[5] Y. Sugawara et al., “12.7kV Ultra High Voltage SiC Commutated Gate Turn-off Thyristor: SICGT,” in 16th International Symposiumon Power Semiconductor Devices & ICs (ISPSD), Kitakyushu, Japan, pp. 365–368, May 2004.
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[7] H. Linewih and S. Dimitrijev, “Channel-Carrier Mobility Parameters for 4H SiC MOSFETs,” in Proceedings of the 23rd InternationalConference on Microelectronics (MIEL), Niš, Yugoslavia, pp. 425–430, May 2002.
[8] “TCAD Simulation of Silicon Carbide Devices: Part I. Models and Parameters,” TCAD News, pp. 3–5, September 2006.
[9] J. H. Zhao et al., “3.6 mΩcm2, 1726 V 4H-SiC normally-off trenched-and-implanted vertical JFETs and circuit applications,”IEE Proceedings – Circuits, Devices and Systems, vol. 151, no. 3, pp. 231–237, 2004.
[10] W. J. Schaffer et al., “Conductivity Anisotropy in Epitaxial 6H and 4H SiC,” in Materials Research Society Symposia Proceedings, vol. 339, pp. 595–600, April 1994.
[11] T. T. Mnatsakanov et al., “Universal Analytical Approximation of the Carrier Mobility in Semiconductors for a Wide Range of Temperatures and Doping Densities,” Semiconductors, vol. 38, no. 1, pp. 56–60, 2004.
[12] T. Hatakeyama et al., “Physical Modeling and Scaling Properties of 4H-SiC Power Devices,” in International Conference onSimulation of Semiconductor Processes and Devices (SISPAD), Tokyo, Japan, pp. 171–174, September 2005.