Nm NMOS Distortion Analysis
The scaling of CMOS technology offered a significant improvement in RF performance in MOS devices. In view of the fast growth of the wireless communication market, designers are exploring conventional CMOS instead of III–V or SiGe in RF circuits. Since system requirements on linearity become more stringent for future wideband RF applications, the inherent superior linearity compared to the faster SiGe BJTs is a significant advantage for CMOS [3].
Figure 5 shows a generic NMOS with a nominal gate length of 65 nm, width of 1 μm, oxide thickness of 2 nm, and substrate doping of 5 x 1017 cm–3. The device is biased to Vds = 1.2 V and is modulated with a gate source voltage of 0.1 V at 1 MHz.
Figure 6 shows the V_IP3 characteristics as a function of the DC gate voltage Vgs for different substrate dopings Ns and oxide
«Fig. 5.» Doping profile of 65 nm NMOS.
«Fig. 6.». Bias dependence of third-order voltage intercept point (V_IP3) for varying substrate dopings and gate oxide thicknesses. Around the threshold voltage, V_IP3 features a peak due to cancellation effects of higher order harmonics.
thicknesses tox. With increasing Vgs, the linearity increases and features a sharp peak around the threshold voltage, which originates from cancellation effects of the higher order harmonics [3][4].
Figure 7 shows the first harmonic of the electron density in a cut through the channel as a function of the DC bias voltage Vgs.
«Fig. 7.». First harmonic component of electron density in NMOS channel. At low DC bias voltage Vgs, the electron density is modulated more strongly at the drain side.
For low bias Vgs, the electron density towards the drain side is modulated remarkably stronger than for high Vgs. This is one cause of the higher distortion at low bias Vgs observed in Figure 6.
The HBM can be used also to investigate high-amplitude modulation conditions such as the 1-dB compression point or the saturation behavior of first-order and third-order modulation products in two-tone experiments.
Figure 8 shows the results of an intermodulation distortion simulation for the 65 nm NMOS with a DC bias Vgs of 0.7 V and f1 = 1 MHz, f2 = 1.001 MHz for increasing modulation amplitude Vg1. For gate voltage modulation amplitudes higher than 0.2 V, saturation of both the fundamental harmonic and the thirdorder modulation products of the drain current increases, limiting the maximum available modulation power.
The examples without matching circuits investigated so far are used mainly for lowfrequency amplification applications
«Fig. 8.».NMOS saturation behavior of fundamental and third-order drain current components for increasing modulation voltage. For modulation amplitudes above 0.2 V, saturation effects start limiting the available current and power gain.
with modulation frequencies below 10% of the transit frequency of the device.
For high-frequency amplification, a suitable matching circuit (reactive or resistive) must be optimized for each specific application. This can be performed also using the HBM where the matching elements are added in a SPICE-like manner.
Conclusion
In summary, the harmonic balance module available in Sentaurus Device opens the possibility to analyze distortion effects at the device level in an efficient way. Applications include harmonic distortion, intermodulation distortion, and signal compression analysis for a wide range of devices using a onedimensional, two-dimensional, or threedimensional geometry, and a mixed-mode simulation setup. Sentaurus Device is the ideal simulation tool for optimization with respect to distortion effects already in the device design phase.
References
[1] B. Troyanovsky, Z. Yu, and R. W. Dutton, “Physics-based simulation of nonlinear distortion in semiconductor devices using the harmonic balance method,” Computer Methods in Applied Mechanics and Engineering, vol. 181, no. 4, pp. 467–482, 2000.
[2] S. Odermatt, B. Witzigmann, and B. Schmithüsen, “Harmonic balance analysis for semiconductor lasers under large-signal modulation,” Optical and Quantum Electronics, vol. 38, no. 12‑14, pp. 1039–1044, 2006.
[3] B. Murmann et al., “Impact of Scaling on Analog Performance and Associated Modeling Needs,” IEEE Transactions on Electron Devices, vol. 53, no. 9, pp. 2160–2167, 2006.
[4] R. van Langevelde et al., “RF-Distortion in Deep-Submicron CMOS Technologies,” in IEDM Technical Digest, San Francisco, CA, USA, pp. 807–810, December 2000.