An Efficient Simulation Environment for Modeling Single Event Effects with the Sentaurus Tool Suite


Introduction

Single event effects (SEEs) in microelectronics are caused when highly energetic particles present in packaging materials, or in natural space and terrestrial environments (for example, protons, neutrons, alpha particles, or heavy ions), strike sensitive regions of a microelectronic circuit [1]. Similar effects can occur also when an incident particle collides with an atom and produces a reaction product capable of depositing a significant amount of energy. Depending on a number of factors, the particle strike can cause no observable effect, or a transient disruption of circuit operation, or a change of logic state, or even permanent damage to the device or integrated circuit (IC) [1]. SEEs have long been a consideration for electronics applications in space environments (where ionizing radiation is abundant) and for some terrestrial electronic applications.

Scaling of CMOS device sizes to nanometer dimensions and low operating voltages mean that the amount of charge associated with ‘bits’ of information, and circuit noise margins, is becoming extremely small. In addition, the high transistor packing density means that a single ionizing particle potentially impacts multiple transistors. All of this increases the challenge of using advanced CMOS technologies in space and radiation environments and elevates SEEs as a major reliability consideration in commercial electronics.

Analysis of SEEs in advanced circuitry involves the determination of the response of multiple interactive devices, coupled with the application-specific overall circuit response, to energy deposition by a particle using ionization or secondary reactions. TCAD and mixed-mode simulations can be used to determine the device and circuit responses to radiation events. The characteristics of the energy deposition produced by the events, as well as the event rates, can be simulated using Monte Carlo codes such as SEMM2 [2] and Geant4-based codes such as MRED [3][4]. The increase in obtainable computing power per cost over recent years enables problems of much larger computational complexity to be examined using such simulations.

In this article, a single-event simulation methodology based on the use of the TCAD Sentaurus Version Z-2007.03 tool suite is presented. To fully characterize SEEs, a systematic and rigorous simulation matrix with more than 100 simulations is needed. The new capabilities in the Sentaurus tool suite allow us to take advantage of a parallel highperformance computing system at Vanderbilt University and to run the simulations efficiently.

We use such simulation capabilities to examine various aspects of SEEs, including chargesharing, the impact of nuclear reactions in the overlayers, and single event transients and upsets [5]. The simulations presented in this article focus on the single event response of a baseline (unhardened) 90-nm SRAM cell designed from a commercial 90-nm process.

Simulation Environment

This work was conducted in part using the resources of the Advanced Computing Center for Research and Education (ACCRE) at Vanderbilt University, Nashville, Tennessee [6]. The ACCRE high-performance computing system consists of approximately 1500 processors and has a capacity of approximately 6 TFLOPS. Each node is built with dual processors, and each processor has at least 1-GB memory. The latest version of the Sentaurus tools allows users to run a TCAD simulation on a node, fully utilizing both processors and all available memory on that node for a single simulation. This provides a significant speedup in simulation time, compared to running the same simulation on a single processor.

Device Simulation

As noted, the small size and proximity of multiple devices requires the modeling of multiple devices using 3D TCAD. A sixtransistor 90-nm SRAM cell has been modeled with the Sentaurus tool suite, as shown in Figure 1. As device sizes shrink, memory

«Fig. 1.»Six-transistor SRAM cell built in a 90-nm process. Circuit schematic represents mixed-mode connections for SRAM cell. Although all six devices are modeled in a single TCAD structure, the nodes are wired up in mixed-mode to allow for voltage perturbations.

cells are becoming much more compact in size, with entire cell areas now comparable to single-transistor drain-node areas of only a few generations ago.

However, the size of the ion-induced charge filament does not scale. In the past, with larger size devices, the simulation of a cell using a single transistor in TCAD, while the others were represented using compact models (that is, mixed mode), provided a reasonably accurate representation of how the circuit would respond to a single event. However, as we move towards more compact circuitry, issues such as multi-node charge collection and parasitic transistor action are important in determining circuit responses [7].

The SRAM cell comprises two NMOS transistors and two PMOS transistors as the cross-coupled inverter pair, and an additional set of two NMOS transistors that are access transistors and are used to read or write the cell. The mesh consists of 85 000 vertices, or 5000 2D elements and 450 000 3D elements. Each NMOS and PMOS transistor is calibrated to SPICE and process data before building the SRAM cell. This ensures a high level of fidelity in the SRAM cell model.

The simulations are all run in the mixed-mode environment, as represented in Figure 1. In this case, the mixed-mode connections are made to allow the cell to operate as it would in real conditions. All transistors are simulated in TCAD, but the mixed-mode connections allow the node voltages to change in response to the ion-induced perturbation and potentially for the cell to flip states, consistent with charge moving through the structure. If all nodes were hardwired to a source, the cell would never change states due to a perturbation. Figure 2

«Fig.2.»Node voltages versus time for bit lines of SRAM cell as a result of a single event strike. In this case, the cell switched states.

shows the response of the bit lines of the SRAM cell following a heavy ion strike to the drain of the off-state NMOS transistor.

Although many of the simulations use the heavy ion statement inside the Sentaurus Device simulator, we have developed an alternative method of depositing charge using the physical model interface (PMI) to Sentaurus. Monte Carlo–based codes (such as Geant4) can provide a realistic distribution of generated charge corresponding to a particular event, rather than an idealized description of an average event. Ions can interact with the Si substrate, dopant atoms, or materials above the active silicon and can cause nuclear reactions [5][8].

The charge distributions generated by these events do not necessarily look like single vector columns of charge. In many cases, the events actually have several ‘fingers’ of charge, as seen in Figure 3.

«Fig.3»Representation of charge generated by a Monte Carlo–based code in whichan ion interacted with materials above the active silicon and showered charge into the device. The output of the Monte Carlo code was used as input to the Sentaurus Device simulation.

Having the capability to analyze these realistic events is vital to understanding how reaction products, including those originating in the overlayer materials, can alter the response of the device or circuit.